View AD5174BCPZ-10-R2_4696544.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Single-Channel, 1024-Position, Digital Rheostat with SPI Interface and 50-TP Memory
AD5174
FEATURES
Single-channel, 1024-position resolution 10 k nominal resistance 50-times programmable (50-TP) wiper memory Rheostat mode temperature coefficient: 35 ppm/C 2.7 V to 5.5 V single-supply operation 2.5 V to 2.75 V dual-supply operation for ac or bipolar operations SPI-compatible interface Wiper setting and memory readback Power on refreshed from memory Resistor tolerance stored in memory Thin LFCSP 10-lead, 3 mm x 3 mmx 0.8 mm package Compact MSOP, 10-lead, 3 mm x 4.9 mm x 1.1 mm package
FUNCTIONAL BLOCK DIAGRAM
VDD
POWER-ON RESET
AD5174
SCLK SYNC DIN SDO SPI SERIAL INTERFACE 10
RDAC REGISTER
A W
50-TP MEMORY BLOCK
APPLICATIONS
Mechanical rheostat replacements Op-amp: variable gain control Instrumentation: gain, offset adjustment Programmable voltage-to-current conversions Programmable filters, delays, time constants Programmable power supply Sensor calibration
VSS
EXT_CAP
GND
Figure 1.
GENERAL DESCRIPTION
The AD5174 is a single-channel, 1024-position digital rheostat that combines industry leading variable resistor performance with nonvolatile memory (NVM) in a compact package. This device supports both dual-supply operation at 2.5 V to 2.75 V and single-supply operation at 2.7 V to 5.5 V and offers 50-times programmable (50-TP) memory. The AD5174 device wiper settings are controllable through the SPI digital interface. Unlimited adjustments are allowed before programming the resistance value into the 50-TP memory. The AD5174 does not require any external voltage supply to facilitate fuse blow and there are 50 opportunities for permanent programming. During 50-TP activation, a permanent blow fuse command freezes the resistance position (analogous to placing epoxy on a mechanical rheostat). The AD5174 is available in a 3 mm x 3mm 10-lead LFCSP package and in a 10-lead MSOP package. The part is guaranteed to operate over the extended industrial temperature range of -40C to +125C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2010 Analog Devices, Inc. All rights reserved.
08718-001
AD5174 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Electrical Characteristics ............................................................. 3 Interface Timing Specifications .................................................. 4 Absolute Maximum Ratings............................................................ 6 Thermal Resistance ...................................................................... 6 ESD Caution .................................................................................. 6 Pin Configuration and Function Descriptions ............................. 7 Typical Performance Characteristics ............................................. 8 Test Circuits ..................................................................................... 11 Theory of Operation ...................................................................... 12 Serial Data Interface ................................................................... 12 Shift Register ............................................................................... 12 RDAC Register............................................................................ 12 50-TP Memory Block ................................................................ 12 Write Protection ......................................................................... 12 RDAC and 50-TP Read Operation .......................................... 13 Shutdown Mode ......................................................................... 14 Reset ............................................................................................. 14 Daisy-Chain Operation ............................................................. 15 RDAC Architecture .................................................................... 15 Programming the Variable Resistor ......................................... 16 EXT_CAP Capacitor.................................................................. 17 Terminal Voltage Operating Range ......................................... 17 Power-Up Sequence ................................................................... 17 Outline Dimensions ....................................................................... 18 Ordering Guide .......................................................................... 18
REVISION HISTORY
3/10--Revision 0: Initial Version
Rev. 0 | Page 2 of 20
AD5174 SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VDD = 2.7 V to 5.5 V, VSS = 0 V; VDD = 2.5 V to 2.75 V, VSS = -2.5 V to -2.75 V; -40C < TA < 125C, unless otherwise noted.
Table 1.
Parameter DC CHARACTERISTICS--RHEOSTAT MODE Resolution Resistor Integral Nonlinearity 2, 3 Symbol Test Conditions/Comments Min 10 -1 -1 -2.5 -1 15 35 35 VSS f = 1 MHz, measured to GND, code = half scale f = 1 MHz, measured to GND, code = half scale VA = VW 90 40 50 Typ 1 Max Unit Bits LSB LSB LSB LSB % ppm/C V pF pF nA
R-INL
|VDD - VSS| = 3.6 V to 5.5 V |VDD - VSS| = 3.3 V to 3.6 V |VDD - VSS| = 2.7 V to 3.3 V
Resistor Differential Nonlinearity2 Nominal Resistor Tolerance Resistance Temperature Coefficient 4, 5 Wiper Resistance RESISTOR TERMINALS Terminal Voltage Range4, 6 Capacitance A4 Capacitance W4 Common-Mode Leakage Current4 DIGITAL INPUTS Input Logic4 High Low Input Current Input Capacitance4 DIGITAL OUTPUT Output Voltage4 High Low
R-DNL Code = full scale Code = zero scale VTERM
+1 +1.5 +2.5 +1
70 VDD
VINH VINL IIN CIN
2.0 0.8 1 5
V V A pF
VOH VOL
RPULL_UP = 2.2 k to VDD RPULL_UP = 2.2 k to VDD VDD = 2.7 V to 5.5 V, VSS = 0 V VDD = 2.5 V to 2.75 V, VSS = -2.5 V to -2.75 V
VDD - 0.1 0.4 0.6 +1 5
V V V A pF V V A A mA mA 500 A A W dB
Tristate Leakage Current Output Capacitance4 POWER SUPPLIES Single-Supply Power Range Dual-Supply Power Range Supply Current Positive Negative 50-TP Store Current4, 7 Positive Negative 50-TP Read Current4, 8 Positive Negative Power Dissipation 9 Power Supply Rejection Ratio4
-1
VSS = 0 V
2.7 2.5
5.5 2.75 1
IDD ISS IDD_OTP_STORE ISS_OTP_STORE IDD_OTP_READ ISS_OTP_READ PDISS PSRR
-1 4 -4
-500 VIH = VDD or VIL = GND VDD/VSS = 5 V 10% 5.5 -50 -55
Rev. 0 | Page 3 of 20
AD5174
Parameter DYNAMIC CHARACTERISTICS4, 10 Bandwidth Total Harmonic Distortion Resistor Noise Density
1 2
Symbol
Test Conditions/Comments -3 dB, RAW = 5 k, Terminal W, see Figure 24 VA = 1 V rms, f = 1 kHz, RAW = 5 k RWB = 5 k, TA = 25C, f = 10 kHz
Min
Typ 1 700 -90 13
Max
Unit kHz dB nV/Hz
Typical specifications represent average readings at 25C, VDD = 5 V, and VSS = 0 V. Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from the ideal between successive tap positions. 3 The maximum current in each code is defined by IAW = (VDD - 1)/RAW. 4 Guaranteed by design and not subject to production test. 5 See Figure 9 for more details. 6 Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground referenced bipolar signal adjustment. 7 Different from operating current; the supply current for the fuse program lasts approximately 55 ms. 8 Different from operating current; the supply current for the fuse read lasts approximately 500 ns. 9 PDISS is calculated from (IDD x VDD) + (ISS x VSS). 10 All dynamic characteristics use VDD = +2.5 V, VSS = -2.5 V.
INTERFACE TIMING SPECIFICATIONS
VDD = 2.7 V to 5.5 V, VSS = 0 V; VDD = 2.5 V, VSS = -2.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 2.
Parameter t1 2 t2 t3 t4 t5 t6 t7 t8 3 t9 t10 4 tMEMORY_READ tMEMORY_PROGRAM tRESET tPOWER-UP 5
1 2 3
Limit 1 20 10 10 15 5 5 1 400 15 450 6 350 600 2
Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min ns max s max ms max s max ms max
Test Conditions/Comments SCLK cycle time SCLK high time SCLK low time SYNC to SCLK falling edge setup time Data setup time Data hold time SCLK falling edge to SYNC rising edge Minimum SYNC high time SYNC rising edge to next SCLK fall ignored SCLK rising edge to SDO valid Memory readback execute time Memory program time Reset OTP restore time Power-on 50-TP restore time
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. Maximum SCLK frequency is 50 MHz. Refer to tMEMORY_READ and tMEMORY_PROGRAM for memory commands operations. 4 RPULL_UP = 2.2 k to VDD with a capacitance load of 168 pF. 5 Maximum time after VDD - VSS is equal to 2.5 V.
Rev. 0 | Page 4 of 20
AD5174
Shift Register and Timing Diagrams
DB9 (MSB) 0 0 C3 C2 C1 C0 D9 D8 D7 D6 D5 D4 D3 D2 D1 DB0 (LSB) D0
DATA BITS CONTROL BITS
Figure 2. Shift Register Content
t4
SCLK
t2
t1
t7
t8
SYNC
t3 t5
t9
t6
D0
DIN
0
0
C3
C2
D7
D6
D5
D2
D1
08718-002
SDO
Figure 3. Write Timing Diagram, CPOL=0, CPHA = 1
SCLK
t9
SYNC
DIN
0
0
C3
D0
D0
0
0
C3
D1
D0
t10
SDO X X C3 D1 D0
08718-004
Figure 4. Read Timing Diagram, CPOL=0, CPHA = 1
Rev. 0 | Page 5 of 20
08718-003
AD5174 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 3.
Parameter VDD to GND VSS to GND VDD to VSS VA, VW to GND Digital Input and Output Voltage to GND EXT_CAP to VSS IA, IW Pulsed 1 Frequency > 10 kHz Frequency 10 kHz Continuous Operating Temperature Range 3 Maximum Junction Temperature (TJ Maximum) Storage Temperature Range Reflow Soldering Peak Temperature Time at Peak Temperature Package Power Dissipation
1
Rating -0.3 V to +7.0 V +0.3 V to -7.0 V 7V VSS - 0.3 V, VDD + 0.3 V -0.3 V to VDD + 0.3 V 7V
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL RESISTANCE
JA is defined by JEDEC specification JESD-51 and the value is dependent on the test board and test environment. Table 4. Thermal Resistance.
Package Type 10-Lead LFCSP 10-Lead MSOP
1
6 mA/d 2 6 mA/d2 6 mA -40C to +125C 150C -65C to +150C 260C 20 sec to 40 sec (TJ max - TA)/JA
JA1 50 135
JC 3 N/A
Unit C/W C/W
JEDEC 2S2P test board, still air (0 m/sec airflow).
ESD CAUTION
Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A and W terminals at a given resistance. 2 Pulse duty factor. 3 Includes programming of 50-TP memory.
Rev. 0 | Page 6 of 20
AD5174 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VDD 1 A2
VDD 1 A W3
2 10
10 SYNC
AD5174
(EXPOSED PAD)*
9 SCLK 8 DIN 7 SDO 6 GND
08718-103
AD5174
TOP VIEW (Not to Scale)
SYNC SCLK DIN GND
08718-005
W3 VSS 4 EXT_CAP 5
9 8 7 6
VSS 4 EXT_CAP 5
SDO
*LEAVE FLOATING OR CONNECTED TO VSS.
Figure 5. MSOP Pin Configuration
Figure 6. LFCSP Pin Configuration
Table 5. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 Mnemonic VDD A W VSS EXT_CAP GND SDO DIN SCLK SYNC Description Positive Power Supply. Decouple this pin with 0.1 F ceramic capacitors and 10 F capacitors. Terminal A of RDAC. VSS VA VDD. Wiper Terminal of RDAC. VSS VW VDD. Negative Supply. Connect to 0 V for single-supply applications. Decouple this pin with 0.1 F ceramic capacitors and 10 F capacitors. External Capacitor. Connect a 1 F capacitor between EXT_CAP and VSS. This capacitor must have a voltage rating of 7 V. Ground Pin, Logic Ground Reference. Serial Data Output. This open-drain output requires an external pull-up resistor. SDO can be used to clock data from the shift register in daisy-chain mode or in readback mode. Serial Data Line. This pin is used in conjunction with the SCLK line to clock data into or out of the 16-bit input register. Serial Clock Input. Data is clocked into the shift register on the falling edge of the serial clock input. Data can be transferred at rates of up to 50 MHz. Falling Edge Synchronization Signal. This is the frame synchronization signal for the input data. When SYNC goes low, it enables the shift register and data is transferred in on the falling edges of the subsequent clocks. The selected register is updated on the rising edge of SYNC following the 16th clock cycle. If SYNC is taken high before the 16th clock cycle, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the RDAC. Leave floating or connected to VSS
EPAD
Exposed Pad
Rev. 0 | Page 7 of 20
AD5174 TYPICAL PERFORMANCE CHARACTERISTICS
0.8 0.6 0.4
CURRENT (mA)
+25C -40C +125C
1.0
VDD/VSS = 5V/0V
0.8
INL (LSB)
0.2 0 -0.2
0.6
0.4
0.2
-0.4 -0.6
0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
08718-014
0
128
256
384
512
640
768
896
1023
CODE (Decimal)
VOLTAGE (V)
Figure 7. R-INL vs. Code vs. Temperature
0.4 0.3 0.2
Figure 10. Supply Current (IDD) vs. Digital Input Voltage
+25C -40C +125C
500 400 300 200
IDD = 5V
DNL (LSB)
CURRENT (nA)
0.1 0 -0.1 -0.2 -0.3
100 0 -100 -200 -300 -400
ISS = 3V
IDD = 3V
ISS = 5V
08718-015
0
128
256
384
512
640
768
896
1023
10 20 30 40 50 60 70 80 90 100 110
CODE (Decimal)
TEMPERATURE (C)
Figure 8. R-DNL vs. Code vs. Temperature
700
Figure 11. Supply Current (IDD, ISS) vs. Temperature
RHEOSTAT MODE TEMPCO (ppm/C)
600 500 400 300 200 100 0
VDD/VSS = 5V/0V
7 6
THEORETICAL lWA_MAX (mA)
VDD/VSS = 5V/0V
5 4 3 2 1
08718-019
0
128
256
384
512
640
768
896
1023
0
85
170 255 340 425 510 595 680 765 850 935 1023 CODE (Decimal)
CODE (Decimal)
Figure 9. Tempco RWA/T vs. Code
Figure 12. Theoretical Maximum Current vs. Code
Rev. 0 | Page 8 of 20
08718-028
0
08718-018
-500 -40 -30 -20 -10 0
08718-023
AD5174
-20
0 -5 -10 -15 0x200 0x100 0x080 0x040 0x020 -30 0x010 -35 -40 -45 -50 1 0x008 0x004 0x002 0x001 10 100 1k 10k VDD/VSS = 5V/0V 100k 1M 10M FREQUENCY (Hz)
-25 -30 -35
VDD/VSS = 5V/0V CODE = HALF SCALE
GAIN (dB)
-20 -25
PSRR (dB)
-40 -45 -50 -55
08718-024
08718-102
08718-031
-60 10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 13. Bandwidth vs. Frequency vs. Code
Figure 16. PSRR vs. Frequency
VDD/VSS = 2.5V CODE = HALF SCALE fIN = 1V rms -20 NOISE BW = 22kHz
7
0
8
-40
VOLTAGE (V)
08718-039
THD + N (dB)
-60
6
-80
5
-100
4 0.07 0.09 0.11 0.13 0.15 0.17 TIME (Seconds)
08718-029
-120
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 14. THD + N vs. Frequency
Figure 17. VEXT_CAP Waveform While Writing Fuse
0
10k
20 10
VDD/VSS = 2.5V IAW = 200A
-20
GLITCH AMPLITUDE (mV)
08718-026
0 -10 -20 -30 -40 -50 -60 -70 -2
THD + N (dB)
-40
-60
-80 V /V = 2.5V DD SS CODE = HALF SCALE fIN = 1kHz NOISE BW = 22kHz -100 0.001 0.01
0.1
1
0
2 TIME (s)
4
AMPLITUDE (V rms)
Figure 15. THD + N vs. Amplitude
Figure 18. Maximum Glitch Energy
Rev. 0 | Page 9 of 20
AD5174
1.0 0.006 0.005 0.5 0.004 0.003 0.002 0.001 0 VDD/VSS = 5V/0V IAW = 10A CODE = HALF SCALE
0
-0.5
-1.0 VDD/VSS = 2.5V IAW = 200A
08718-100
0
10
20
30
40
50
60
0
100
200
300
400
500
600
700
800
900
1000
TIME (s)
OPERATION AT 150C (Hours)
Figure 19. Digital Feedthrough
Figure 20. Long-Term Drift Accelerated Average by Burn-In
Rev. 0 | Page 10 of 20
08718-101
-1.5 -10
RAW RESISTANCE (%)
VOLTAGE (mV)
-0.001 -0.002
AD5174 TEST CIRCUITS
Figure 21 to Figure 25 define the test conditions used in the Specifications section.
DUT W A
08718-033
IW
DUT W A VMS 1G V
Figure 21. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL)
Figure 24. Gain vs. Frequency
VMS RWA = IW DUT CODE = 0x00 W A
08718-034
DUT W A ICM
GND +2.75V -2.75V GND
08718-037
IW
RW =
RWA 2
VMS
NC +2.75V
GND -2.75V
NC = NO CONNECT
Figure 22. Wiper Resistance
Figure 25. Common Leakage Current
V+ = VDD 10% PSRR (dB) = 20 log VDD V+ A IW W VMS PSS (%/%) = VMS% VDD%
VMS VDD
Figure 23. Power Supply Sensitivity (PSS, PSRR)
08718-035
Rev. 0 | Page 11 of 20
08718-036
VMS
AD5174 THEORY OF OPERATION
The AD5174 is designed to operate as a true variable resistor for analog signals within the terminal voltage range of VSS < VTERM < VDD. The RDAC register contents determine the resistor wiper position. The RDAC register acts as a scratchpad register, which allows unlimited changes of resistance settings. The RDAC register can be programmed with any position setting by using the SPI interface. When a desirable wiper position is found, this value can be stored in a 50-TP memory register. Thereafter, the wiper position is always restored to that position for subsequent power-ups. The storing of 50-TP data takes approximately 350 ms; during this time, the AD5174 locks to prevent any changes from taking place. The AD5174 also feature a patented 1% end-to-end resistor tolerance. This simplifies precision, rheostat mode, and openloop applications where knowledge of absolute resistance is critical.
RDAC REGISTER
The RDAC register directly controls the position of the digital rheostat wiper. For example, when the RDAC register is loaded with all 0s, the wiper is connected to Terminal A of the variable resistor. The RDAC register is a standard logic register, and there is no restriction on the number of changes allowed. The basic mode of setting the variable resistor wiper position (programming the RDAC register) is accomplished by loading the serial data input register with Command 1 (see Table 6) and with the desired wiper position data.
50-TP MEMORY BLOCK
The AD5174 contains an array of 50-TP programmable memory registers, which allow the wiper position to be programmed up to 50 times. Table 10 shows the memory map. When the desired wiper position is determined, the user can load the serial data input register with Command 3 (see Table 6), which stores the wiper position data in a 50-TP memory register. The first address to be programmed is Location 0x01 (see Table 10); the AD5174 increments the 50-TP memory address for each subsequent program until the memory is full. Programming data to 50-TP consumes approximately 4 mA for 55 ms, and takes approximately 350 ms to complete, during which time the shift register locks to prevent any changes from occurring. Bit C2 of the control register can be polled to verify that the fuse program command was completed properly. No change in supply voltage is required to program the 50-TP memory; however, a 1 F capacitor on the EXT_CAP pin is required (see Figure 28). Prior to 50-TP activation, the AD5174 presets to midscale on power-up.
SERIAL DATA INTERFACE
The AD5174 contains a serial interface (SYNC, SCLK, DIN, and SDO) that is compatible with SPI interface standards, as well as most DSPs. This device allows writing of data via the serial interface to every register.
SHIFT REGISTER
The shift register is 16 bits wide, as shown in Figure 2. The 16-bit word consists of two unused bits, which should be set to 0, followed by four control bits and 10 RDAC data bits. Data is loaded MSB first (Bit D9). The four control bits determine the function of the software command as listed in Table 6. Figure 3 shows a timing diagram of a typical AD5174 write sequence. The write sequence begins by bringing the SYNC line low. The SYNC pin must be held low until the complete data-word is loaded from the DIN pin. When SYNC returns high, the serial data-word is decoded according to the instructions in Table 6. The command bits (Cx) control the operation of the digital potentiometer. The data bits (Dx) are the values that are loaded into the decoded register. The AD5174 has an internal counter that counts a multiple of 16 bits (a frame) for proper operation. For example, AD5174 works with a 32-bit word but does not work properly with a 31-bit or 33-bit word. The AD5174 does not require a continuous SCLK when SYNC is high. To minimize power consumption in the digital input buffers, operate all serial interface pins close to the VDD supply rails.
WRITE PROTECTION
At power-up, the serial data input register write commands for both the RDAC register and the 50-TP memory registers are disabled. The RDAC write protect bit, C1, of the control register (see Table 8 and Table 9) is set to 0 by default. This disables any change of the RDAC register content regardless of the software commands, except that the RDAC register can be refreshed from the 50-TP memory using the software reset, Command 4 (see Table 6). To enable programming of the RDAC register, the write protect bit (Bit C1), of the control register must first be programmed by loading the serial data input register with Command 7. To enable programming of the 50-TP memory, the program enable bit (Bit C0) of the control register, which is set to 0 by default, must first be set to 1.
Rev. 0 | Page 12 of 20
AD5174
RDAC AND 50-TP READ OPERATION
A serial data output SDO pin is available for readback of the internal RDAC register or 50-TP memory contents. The contents of the RDAC register can be read back through SDO by using Command 2 (see Table 6). Data from the RDAC register is clocked out of the SDO pin during the last 10 clocks of the next SPI operation. It is possible to read back the contents of any of the 50-TP memory registers through SDO by using Command 5. The lower six LSB bits, D5 to D0 of the data byte, select which memory location is to be read back, as shown in Table 10. Table 6. Command Operation Truth Table
Command Number 0 1 2 3 4 52 6 73 8 9 Command[DB13:DB10] C3 C2 C1 C0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 D9 X D9 X X X X X X X X D8 X D8 X X X X X X X X D7 X D7 X X X X X X X X Data[DB9:DB0] 1 D6 D5 D4 D3 X X X X D6 D5 D4 D3 X X X X X X X X X X X D5 X X X X X X X D4 X X X X X X X D3 X X X X D2 X D2 X X X D2 X X X X D1 X D1 X X X D1 X D1 X X D0 X D0 X X X D0 X D0 X D0 Operation NOP: do nothing. Write contents of serial register data to RDAC. Read contents of RDAC wiper register. Store wiper setting: store RDAC setting to 50-TP. Software reset: refresh RDAC with last 50-TP memory stored value. Read contents of 50-TP from SDO output in the next frame. Read address of last 50-TP programmed memory location. Write contents of serial register data to control register. Read contents of control register. Software shutdown. D0 = 0; normal mode. D0 = 1; device placed in shutdown mode.
Data from the selected memory location is clocked out of the SDO pin during the next SPI operation. A binary encoded version address of the most recently programmed wiper memory location can be read back using Command 6 (see Table 6). This can be used to monitor the spare memory status of the 50-TP memory block. Table 7 provides a sample listing for the sequence of serial data input (DIN) words with the serial data output appearing at the SDO pin in hexadecimal format for a write and read to both the RDAC register and the 50-TP memory (Memory Location 20).
1 2
X is don't care. See Table 10 for 50-TP memory map. 3 See Table 9 for bit details.
Rev. 0 | Page 13 of 20
AD5174
SHUTDOWN MODE
The AD5174 can be shut down by executing the software shutdown command, Command 9 (see Table 6), and setting the LSB to 1. This feature places the RDAC in a zero-powerconsumption state where Terminal A is open circuited and the wiper terminal, W, remains connected. It is possible to execute any command from Table 6 while the AD5174 is in shutdown mode. The parts can be taken out of shutdown mode by executing Command 9 and setting the LSB to 0 or by a software reset, Command 4 (see Table 6). Table 7. Write and Read to RDAC and 50-TP Memory
DIN 0x1C03 0x0500 0x0800 0x0C00 0x1800 0x0000 0x1419 0x2000 0x0000
1
RESET
The AD5174 can be reset through software by executing Command 4 (see Table 6). The reset command loads the RDAC register with the contents of the most recently programmed 50-TP memory location. The RDAC register loads with midscale if no 50-TP memory location has been previously programmed.
SDO 1 0xXXXX 0x1C03 0x0500 0x100 0x0C00 0xXX19 0x0000 0x0100 0xXXXX
Action Enable update of the wiper position and the 50-TP memory contents through the digital interface. Write 0x100 to the RDAC register; wiper moves to 1/4 full-scale position. Prepares data read from RDAC register. Stores RDAC register content into the 50-TP memory. A 16-bit word appears out of SDO, where the last 10 bits contain the contents of the RDAC register (0x100). Prepares data read of the last programmed 50-TP memory monitor location. NOP Instruction 0 sends a 16-bit word out of SDO, where the six LSBs (that is, last six bits) contain the binary address of the last programmed 50-TP memory location, for example, 0x19 (see Table 10). Prepares data read from Memory Location 0x19. Prepares data read from the control register. Sends a 16-bit word out of SDO, where the last 10 bits contain the contents of Memory Location 0x19. NOP Instruction 0 sends a 16-bit word out of SDO, where the last four bits contain the contents of the control register. If Bit C2 = 1, the fuse program command was successful.
X is don't care.
Table 8. Control Register Bit Map
D9 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 C2 D2 0 D1 C1 D0 C0
Table 9. Control Register Bit Description
Bit Name C0 Description 50-TP program enable 0 = 50-TP program disabled (default) 1 = enable device for 50-TP program RDAC register write protect 0 = wiper position frozen to value in 50-TP memory (default) 1 1 = allow update of wiper position through digital interface 50-TP memory program success bit 0 = fuse program command was unsuccessful (default) 1 = fuse program command was successful
C1
C2
1
Wiper position frozen to the last value programmed in the 50-TP memory. The wiper is frozen to midscale if the 50-TP memory has not been previously programmed.
Rev. 0 | Page 14 of 20
AD5174
Table 10. Memory Map
Command Number 5 D9 X X X X X ... X ... X ... X ... X ... X ... X X D8 X X X X X ... X ... X ... X ... X ... X ... X X D7 X X X X X ... X ... X ... X ... X ... X ... X X Data Byte[DB9:DB0] 1 D6 D5 D4 D3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ... ... ... ... 0 0 0 1 ... ... ... ... 0 0 1 0 ... ... ... ... 0 0 1 1 ... ... ... ... 0 1 0 1 ... ... ... ... 0 1 1 0 ... ... ... ... 0 1 1 1 0 1 1 1 D2 0 0 0 0 1 ... 0 ... 1 ... 1 ... 0 ... 0 ... 0 0 D1 0 0 1 1 0 ... 1 ... 0 ... 1 ... 0 ... 1 ... 0 1 D0 0 1 0 1 0 ... 0 ... 0 ... 0 ... 0 ... 0 ... 1 0 Register Contents Reserved 1st programmed wiper location (0x01) 2nd programmed wiper location (0x02) 3rd programmed wiper location (0x03) 4th programmed wiper location (0x04) ... 10th programmed wiper location (0xA) ... 20th programmed wiper location (0x14) ... 30th programmed wiper location (0x1E) ... 40th programmed wiper location (0x28) ... 50th programmed wiper location (0x32) ... MSB resistance tolerance (0x39) LSB resistance tolerance (0x3A)
1
X is don't care.
DAISY-CHAIN OPERATION
The serial data output pin (SDO) serves two purposes: it can be used to read the contents of the wiper setting and 50-TP values using Command 2 and Command 5, respectively (see Table 6), or the SDO pin can be used in daisy-chain mode. The remaining instructions are valid for daisy chaining multiple devices in simultaneous operations. Data is clocked out of SDO on the rising edge of SCLK. Daisy chaining minimizes the number of port pins required from the controlling IC. The SDO pin contains an open-drain N-channel FET that requires a pull-up resistor if this pin is used. As shown in Figure 26, users need to tie the SDO pin of one package to the DIN pin of the next package. Users may need to increase the clock period, because the pull-up resistor and the capacitive loading at the SDO-toDIN interface may require additional time delay between subsequent devices. When two AD5174 devices are daisychained, 32 bits of data are required. The first 16 bits go to U2, and the second 16 bits go to U1. Keep the SYNC pin low until all 32 bits are clocked into their respective serial registers. The SYNC pin is then pulled high to complete the operation.
VDD
RDAC ARCHITECTURE
To achieve optimum performance, Analog Devices, Inc., has patented the RDAC segmentation architecture for all the digital potentiometers. In particular, the AD5174 employs a three-stage segmentation approach as shown in Figure 27. The AD5174 wiper switch is designed with the transmission gate CMOS topology.
A
RL
RL
RM
10-BIT ADDRESS DECODER
RM RW
SW
W RW
08718-007
Figure 27. Simplified RDAC Circuit
AD5174 U1
MOSI C SCLK SS SYNC SCLK DIN SDO
RP 2.2k
AD5174 U2
DIN SDO
SYNC SCLK
08718-006
Figure 26. Daisy-Chain Configuration Using SDO
Rev. 0 | Page 15 of 20
AD5174
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The nominal resistance between Terminal W and Terminal A, RWA, is 10 k and has 1024-tap points accessed by the wiper terminal. The 10-bit data in the RDAC latch is decoded to select one of the 1024 possible wiper settings. As a result, the general equation for determining the digitally programmed output resistance between the W terminal and the A terminal is
Calculate the Actual End-to-End Resistance
The resistance tolerance is stored in the internal memory during factory testing. The actual end-to-end resistance can, therefore, be calculated (which is valuable for calibration, tolerance matching, and precision applications). The resistance tolerance (in percentage) is stored in fixed-point format, using a 16-bit sign magnitude binary. The sign bit(0 = negative and 1 = positive) and the integer part is located in Address 0x39 as shown in Table 10. Address 0x3A contains the fractional part as shown in Table 11. That is, if the data readback from Address 0x39 is 0000001010 and data from Address 0x3A is 0010110000, then the end-to-end resistance can be calculated as follows. For Memory Location 0x39, DB[9:8]: XX = don't care DB[7]: 0 = negative DB[6:0]: 0001010 = 10 For Memory Location 0x3A, DB[9:8]: XX = don't care DB[7:0]: 10110000 = 176 x 2-8 = 0.6875 Therefore, tolerance = -10.6875% and RWA (1023)= 8.931 k.
RWA (D) =
D x RWA 1024
(1)
where: D is the decimal equivalent of the binary code loaded in the 10-bit RDAC register. RWA is the end-to-end resistance. In the zero-scale condition, a finite total wiper resistance of 120 is present. Regardless of which setting the part is operating in, take care to limit the current between Terminal A and Terminal W to the maximum continuous current of 6 mA or a pulse current specified in Table 3. Otherwise, degradation or possible destruction of the internal switch contact may occur.
Table 11. End-to-End Resistance Tolerance Bytes
Memory Map Address 0x39 0x3A
1
DB9 X X
DB8 X X
DB7 Sign 2-1
DB6 26 2-2
Data Byte 1 DB5 DB4 25 24 2-3 2-4
DB3 23 2-5
DB2 22 2-6
DB1 21 2-7
DB0 20 2-8
X is don't care.
Rev. 0 | Page 16 of 20
AD5174
EXT_CAP CAPACITOR
A 1 F capacitor to VSS must be connected to the EXT_CAP pin, as shown in Figure 28, on power-up and throughout the operation of the AD5174.
AD5174
50-TP MEMORY BLOCK VSS
08718-008
EXT_CAP C1 1F
The ground pin of the AD5174 is primarily used as a digital ground reference. To minimize the digital ground bounce, join the AD5174 ground terminal remotely to the common ground. The digital input control signals to the AD5174 must be referenced to the device ground pin (GND) and must satisfy the logic level defined in the Specifications section. An internal level shift circuit ensures that the common-mode voltage range of the three terminals extends from VSS to VDD, regardless of the digital input level.
POWER-UP SEQUENCE
Because there are diodes to limit the voltage compliance at Terminal A and Terminal W (see Figure 29), it is important to power VDD/VSS first before applying any voltage to Terminal A and Terminal W; otherwise, the diode is forward-biased such that VDD/VSS are powered unintentionally. The ideal powerup sequence is VSS, GND, VDD, digital inputs, VA, and VW. The order of powering VA, VW, and the digital inputs is not important as long as they are powered after VDD/VSS. As soon as VDD is powered, the power-on preset activates, which first sets the RDAC to midscale and then restores the last programmed 50-TP value to the RDAC register.
VSS
Figure 28. EXT_CAP Hardware Setup
TERMINAL VOLTAGE OPERATING RANGE
The positive VDD and negative VSS power supplies of the AD5174 define the boundary conditions for proper 2-terminal digital resistor operation. Supply signals present on Terminal A and Terminal W that exceed VDD or VSS are clamped by the internal forward-biased diodes (see Figure 29).
VDD
A W
VSS
Figure 29. Maximum Terminal Voltages Set by VDD and VSS
08718-009
Rev. 0 | Page 17 of 20
AD5174 OUTLINE DIMENSIONS
3.10 3.00 SQ 2.90
6
2.48 2.38 2.23 0.50 BSC
10 EXPOSED PAD
PIN 1 INDEX AREA 0.50 0.40 0.30
TOP VIEW
1.74 1.64 1.49
5 BOTTOM VIEW
1
PIN 1 INDICATOR (R 0.15)
0.80 0.75 0.70 SEATING PLANE 0.30 0.25 0.20
0.05 MAX 0.02 NOM
FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
121009-A
0.20 REF
Figure 30. 10-Lead Frame Chip Scale Package [LFCSP_WD] 3 mm x 3mm Body, Very Thin, Dual Lead (CP-10-9) Dimensions shown in millimeters
3.10 3.00 2.90
10
6
3.10 3.00 2.90 PIN 1 IDENTIFIER
1
5.15 4.90 4.65
5
0.50 BSC 0.95 0.85 0.75 0.15 0.05 COPLANARITY 0.10 0.30 0.15 15 MAX 1.10 MAX 0.70 0.55 0.40
091709-A
6 0
0.23 0.13
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 31. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters
ORDERING GUIDE
Model1 AD5174BRMZ-10 AD5174BRMZ-10-RL7 AD5174BCPZ-10-R2 AD5174BCPZ-10-RL7
1
RAB (k) 10 10 10 10
Resolution 1,024 1,024 1,024 1,024
Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C
Package Description 10-Lead MSOP 10-Lead MSOP 10-Lead LFCSP_WD 10-Lead LFCSP_WD
Package Option RM-10 RM-10 CP-10-9 CP-10-9
Branding DDT DDT DEF DEF
Z = RoHS Compliant Part.
Rev. 0 | Page 18 of 20
AD5174 NOTES
Rev. 0 | Page 19 of 20
AD5174 NOTES
(c)2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08718-0-3/10(0)
Rev. 0 | Page 20 of 20

▲Up To Search▲

Price & Availability of AD5174BCPZ-10-R2

	To Download AD5174BCPZ-10-R2 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .